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DATE
2006
IEEE
171views Hardware» more  DATE 2006»
13 years 11 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
13 years 11 months ago
Two-phase resonant clocking for ultra-low-power hearing aid applications
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...
Flavio Carbognani, Felix Bürgin, Norbert Felb...
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
13 years 11 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
DATE
2006
IEEE
75views Hardware» more  DATE 2006»
13 years 11 months ago
GALS networks on chip: a new solution for asynchronous delay-insensitive links
In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtai...
G. Campobello, M. Castano, C. Ciofi, Daniele Manga...
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
13 years 11 months ago
A mixed-signal verification kit for verification of analogue-digital circuits
This paper presents an innovative approach for analogue and mixed-signal verification. It consists in a “verification kit” that makes use of concepts used in state-of-art digi...
Giuseppe Bonfini, Monica Chiavacci, Riccardo Maria...
DATE
2006
IEEE
150views Hardware» more  DATE 2006»
13 years 11 months ago
Advanced receiver algorithms for MIMO wireless communications
Andreas Burg, Moritz Borgmann, Markus Wenk, Christ...
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
13 years 11 months ago
A practical method to estimate interconnect responses to variabilities
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the ...
Frank Liu
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
13 years 11 months ago
Disclosing the LDPC code decoder design space
The design of future communication systems with high throughput demands will become a critical task, especially when sophisticated channel coding schemes have to be applied. LDPC ...
Torben Brack, Frank Kienle, Norbert Wehn
DATE
2006
IEEE
103views Hardware» more  DATE 2006»
13 years 11 months ago
Novel designs for thermally robust coplanar crossing in QCA
In this paper, different circuit arrangements of Quantumdot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. These arrangements exploit the majority votin...
Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, ...