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DATE
2008
IEEE
121views Hardware» more  DATE 2008»
13 years 11 months ago
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
DATE
2008
IEEE
110views Hardware» more  DATE 2008»
13 years 11 months ago
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA
Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin...
DATE
2008
IEEE
91views Hardware» more  DATE 2008»
13 years 11 months ago
Integrated approach to energy harvester mixed technology modelling and performance optimisation
This paper presents an integrated approach to energy harvester modelling and performance optimisation where the complete mixed physical-domain energy harvester system (micro gener...
Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashim...
DATE
2008
IEEE
84views Hardware» more  DATE 2008»
13 years 11 months ago
Physically-Aware N-Detect Test Pattern Selection
N-detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of Ndetect test do not necessarily exploit the localized characte...
Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D...
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
13 years 11 months ago
Power Balanced Gates Insensitive to Routing Capacitance Mismatch
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
13 years 11 months ago
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
Madhura Purnaprajna, Christoph Puttmann, Mario Por...
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
13 years 11 months ago
Logical Reliability of Interacting Real-Time Tasks
We propose the notion of logical reliability for real-time program tasks that interact through periodically updated program variables. We describe a reliability analysis that chec...
Krishnendu Chatterjee, Arkadeb Ghosal, Thomas A. H...
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
13 years 11 months ago
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters
– A new approach for diagnostic analysis of static errors in multi-step ADC based on the steepestdescent method is proposed. To set initial data, estimate the parameter update an...
Amir Zjajo, José Pineda de Gyvez
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
13 years 11 months ago
A Formal Approach To The Protocol Converter Problem
In the absence of a single module interface standard, integration of pre-designed modules in System-on-Chip design often requires the use of protocol converters. Existing approach...
Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Rames...
DATE
2008
IEEE
109views Hardware» more  DATE 2008»
13 years 11 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...