Sciweavers

DAC
2006
ACM
14 years 5 months ago
Programming models and HW-SW interfaces abstraction for multi-processor SoC
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
Ahmed Amine Jerraya, Aimen Bouchhima, Fréd&...
DAC
2006
ACM
14 years 5 months ago
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
DAC
2006
ACM
14 years 5 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
DAC
2006
ACM
14 years 5 months ago
Backlight dimming in power-aware mobile displays
Ali Iranli, Wonbok Lee, Massoud Pedram
DAC
2006
ACM
14 years 5 months ago
Register binding for clock period minimization
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei...
DAC
2006
ACM
14 years 5 months ago
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
Hao Hua, Christopher Mineo, Kory Schoenfliess, Amb...
DAC
2006
ACM
14 years 5 months ago
Communication latency aware low power NoC synthesis
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham...
DAC
2006
ACM
14 years 5 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
DAC
2006
ACM
14 years 5 months ago
Fast algorithms for slew constrained minimum cost buffering
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K...
DAC
2006
ACM
14 years 5 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...