DAC
2006
ACM
14 years 5 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Graphics-intensive computer games are no longer restricted to highperformance desktops, but are also available on a variety of portable devices ranging from notebooks to PDAs and ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...