DAC
2004
ACM
13 years 10 months ago
2004
ACM
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
MSE
2005
IEEE
13 years 10 months ago
2005
IEEE
The fast growing complexity and short time-tomarket of embedded systems designs, besides the great increase in capacity of today’s chips, are mobilizing the industry towards to ...
DFT
2005
IEEE
13 years 10 months ago
2005
IEEE
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require devel...
FDL
2006
IEEE
13 years 11 months ago
2006
IEEE
Needs in the worldwide competition push teams to master more and more their design flow in order to minimize risks, costs, time to market, and potential liabilities. The classical...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...