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ATS
2010
IEEE
250views Hardware» more  ATS 2010»
10 years 1 months ago
Efficient Embedding of Deterministic Test Data
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson,...
ATS
2004
IEEE
93views Hardware» more  ATS 2004»
10 years 8 months ago
Hybrid BIST Test Scheduling Based on Defect Probabilities
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
ATS
1998
IEEE
91views Hardware» more  ATS 1998»
10 years 8 months ago
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
10 years 10 months ago
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use clus...
Lei Li, Krishnendu Chakrabarty
DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
10 years 10 months ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
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