ATS
2010
IEEE
13 years 1 months ago
2010
IEEE
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
ATS
1998
IEEE
13 years 8 months ago
1998
IEEE
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use clus...
DDECS
2006
IEEE
13 years 10 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...