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ISLPED
1995
ACM
113views Hardware» more  ISLPED 1995»
10 years 6 months ago
Low delay-power product CMOS design using one-hot residue coding
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
William A. Chren Jr.
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
10 years 7 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
10 years 7 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
ISCAS
2005
IEEE
121views Hardware» more  ISCAS 2005»
10 years 8 months ago
A low-power high-SFDR CMOS direct digital frequency synthesizer
—A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters sel...
Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
ISCAS
2007
IEEE
139views Hardware» more  ISCAS 2007»
10 years 8 months ago
A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
—The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the QuasiLinear interpolation (QLIP) method. The four-segment QLIP is utilized...
Ashkan Ashrafi, Aleksandar Milenkovic, Reza R. Adh...
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