ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
GLVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters sel...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
—The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the QuasiLinear interpolation (QLIP) method. The four-segment QLIP is utilized...