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DSD
2008
IEEE
124views Hardware» more  DSD 2008»
13 years 11 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
DSD
2008
IEEE
115views Hardware» more  DSD 2008»
13 years 11 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
Petr Fiser, Pavel Kubalík, Hana Kubatova
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
13 years 11 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter
DSD
2008
IEEE
125views Hardware» more  DSD 2008»
13 years 11 months ago
On the Complexity of Error Detection Functions for Redundant Residue Number Systems
This paper considers a single-digit error detection in a Redundant Residue Number System (RRNS). Let f be the function that denotes the set of legitimate codes of an RRNS. To anal...
Tsutomu Sasao, Yukihiro Iguchi
DSD
2008
IEEE
107views Hardware» more  DSD 2008»
13 years 11 months ago
Acceleration of Smith-Waterman using Recursive Variable Expansion
Zubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir ...
DSD
2008
IEEE
94views Hardware» more  DSD 2008»
13 years 11 months ago
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip
Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication inte...
Gottfried Fuchs, Matthias Függer, Ulrich Schm...
DSD
2008
IEEE
166views Hardware» more  DSD 2008»
13 years 11 months ago
Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks
Abstract—In two recent contributions [1], [2], we have provided a comparative analysis of various optimization algorithms, which can be used for atomic location estimation, and s...
Stefano Tennina, Marco Di Renzo, Fabio Graziosi, F...
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
13 years 11 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...
DSD
2008
IEEE
84views Hardware» more  DSD 2008»
13 years 11 months ago
A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors
An architecture and VLSI implementation of a new block cipher called Curupira is presented in this paper. This cipher is suitable for wireless sensors and RFID applications. Our 0...
Paris Kitsos, George N. Selimis, Odysseas G. Koufo...
DSD
2008
IEEE
131views Hardware» more  DSD 2008»
13 years 11 months ago
PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems
In this paper, we examine the digital hardware design and implementation of a novel compact block cipher, referred to as PUFFIN, that is suitable for embedded applications. An imp...
Huiju Cheng, Howard M. Heys, Cheng Wang