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INFOCOM
2012
IEEE
8 years 6 months ago
SpeedBalance: Speed-scaling-aware optimal load balancing for green cellular networks
—This paper considers a component-level deceleration technique in BS operation, called speed-scaling, that is more conservative than entirely shutting down BSs, yet can conserve ...
Kyuho Son, Bhaskar Krishnamachari
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
10 years 2 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong
FPL
2008
Springer
104views Hardware» more  FPL 2008»
10 years 5 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
FPL
2008
Springer
129views Hardware» more  FPL 2008»
10 years 5 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
CF
2005
ACM
10 years 6 months ago
Skewed caches from a low-power perspective
The common approach to reduce cache conflicts is to increase the associativity. From a dynamic power perspective this associativity comes at a high cost. In this paper we present...
Mathias Spjuth, Martin Karlsson, Erik Hagersten
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
10 years 9 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
SLIP
2004
ACM
10 years 9 months ago
Interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum ...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
10 years 9 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
10 years 10 months ago
A timing dependent power estimation framework considering coupling
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and ...
Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, H...
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
10 years 10 months ago
Transition-aware decoupling-capacitor allocation in power noise reduction
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang
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