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ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
9 years 4 months ago
New efficient algorithms for computing effective capacitance
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
Andrew B. Kahng, Sudhakar Muddu
VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
9 years 5 months ago
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
Andrew B. Kahng, Sudhakar Muddu
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
9 years 6 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
Magdy A. El-Moursy, Eby G. Friedman
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
9 years 7 months ago
A More Effective CEFF
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
Sani R. Nassif, Zhuo Li
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