EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: This paper introduces a modified relaxation approach that allows to improve the convergence of iterations while analyzing mixed systems with different simulators. The method redu...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...