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EURODAC
1995
IEEE
149views VHDL» more  EURODAC 1995»
9 years 10 months ago
Cosimulation of real-time control systems
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...
Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrj...
EURODAC
1995
IEEE
150views VHDL» more  EURODAC 1995»
9 years 10 months ago
A reuse scenario for the VHDL-based hardware design flow
Viktor Preis, Renate Henftling, Markus Schütz...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
9 years 10 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
EURODAC
1995
IEEE
134views VHDL» more  EURODAC 1995»
9 years 10 months ago
Area efficient DSP datapath synthesis
Andrew A. Duncan, David C. Hendry
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
9 years 10 months ago
Creating hierarchy in HDL-based high density FGPA design
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
Carol A. Fields
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
9 years 10 months ago
Scalable performance scheduling for hardware-software cosynthesis
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
Thomas Benner, Rolf Ernst, Achim Österling
EURODAC
1995
IEEE
136views VHDL» more  EURODAC 1995»
9 years 10 months ago
Computing subsets of equivalence classes for large FSMs
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
EURODAC
1995
IEEE
116views VHDL» more  EURODAC 1995»
9 years 10 months ago
An improved relaxation approach for mixed system analysis with several simulation tools
: This paper introduces a modified relaxation approach that allows to improve the convergence of iterations while analyzing mixed systems with different simulators. The method redu...
Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
9 years 10 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
9 years 10 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
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