FDL
2007
IEEE
13 years 8 months ago
2007
IEEE
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
FDL
2007
IEEE
13 years 8 months ago
2007
IEEE
Transaction-level modelling (TLM) is a poorlyterm, promising a level of abstraction like RTL (register transfer level), where the key feature is a `transaction'. But unlike r...
FDL
2007
IEEE
13 years 8 months ago
2007
IEEE
In this paper, we propose a domain specific language for the development of hardware/software cryptographic systems based on the well known Python programming language. It is desi...
FDL
2007
IEEE
13 years 8 months ago
2007
IEEE
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
FDL
2007
IEEE
13 years 8 months ago
2007
IEEE
Functional validation of microprocessors is growing in complexity in current and future microprocessors. The informal specification document from which the various collaterals are ...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An im...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
The forthcoming OMG UML Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) aims, amongst other things, at providing a referential Time Model subprofile wher...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...