Sciweavers

Share
FDL
2007
IEEE
9 years 9 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
FDL
2007
IEEE
9 years 9 months ago
Transaction Level Modelling: A reflection on what TLM is and how TLMs may be classified
Transaction-level modelling (TLM) is a poorlyterm, promising a level of abstraction like RTL (register transfer level), where the key feature is a `transaction'. But unlike r...
Mark Burton, James Aldis, Robert Günzel, Wolf...
FDL
2007
IEEE
9 years 9 months ago
A Domain Specific Language for Cryptography
In this paper, we propose a domain specific language for the development of hardware/software cryptographic systems based on the well known Python programming language. It is desi...
Giovanni Agosta, Gerardo Pelosi
FDL
2007
IEEE
9 years 9 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
FDL
2007
IEEE
9 years 9 months ago
A Metamodeling based Framework for Architectural Modeling and Simulator Generation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. The informal specification document from which the various collaterals are ...
Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shu...
FDL
2007
IEEE
10 years 6 days ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
FDL
2007
IEEE
10 years 6 days ago
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
Daniel Große, Hernan Peraza, Wolfgang Klinga...
FDL
2007
IEEE
10 years 6 days ago
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations
Abstract This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An im...
Leran Wang, Chenxu Zhao, Tom J. Kazmierski
FDL
2007
IEEE
10 years 6 days ago
Modeling of immediate vs. delayed data communications: from AADL to UML Marte
The forthcoming OMG UML Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) aims, amongst other things, at providing a referential Time Model subprofile wher...
Frédéric Mallet, Charles André...
FDL
2007
IEEE
10 years 6 days ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
books