FPL
2006
Springer
13 years 8 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
An intermediate representation (IR) is a central structure around which tools such as compilers and synthesis tools are built. In this paper we propose such an IR specifically des...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
FPL
2006
Springer
13 years 8 months ago
2006
Springer
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
An improved FPGA implementation of an electronic cochlea filter is presented. We show that by using decimation, the computations of the electronic cochlea can be reduced. Furtherm...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...