FPL
2009
Springer
13 years 9 months ago
2009
Springer
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
FPL
2009
Springer
13 years 9 months ago
2009
Springer
FPL
2009
Springer
13 years 9 months ago
2009
Springer
A simple image-processing application is implemented on the Ambric MPPA and an FPGA, using a similar implementation for both devices. FPGAs perform extremely well on this kind of ...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, Single Step Segmented Least Recently Used (S3 -LRU) policy, is a netwo...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...