ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clockless) control circuits. Because speed-independent circuits are hazard-free...
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from bein...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...