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8

DATE
2000
IEEE

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Static Timing Analysis Taking Crosstalk into Account

13 years 8 months ago

Static Timing Analysis Taking Crosstalk into Account

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Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates the longest path of synchronous circuits taking the impact of crosstalk on gate delays into account. We show that passive modeling of the coupling capacitance can significantly underestimate the delay and that an assumption of permanent worst-case coupling unnecessarily overestimates it. Our method is validated by comparison to Spice simulations.

Matthias Ringe, Thomas Lindenkreuz, Erich Barke

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Capacitance Coupling | DATE 2000 | Deep Submicron Circuits | Gate Delays | Hardware |

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Added	30 Jul 2010
Updated	30 Jul 2010
Type	Conference
Year	2000
Where	DATE
Authors	Matthias Ringe, Thomas Lindenkreuz, Erich Barke

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