Sciweavers

GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
13 years 10 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
13 years 10 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Mixing ATPG and property checking for testing HW/SW interfaces
A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but ...
Alessandro Fin, Franco Fummi, Graziano Pravadelli
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Variable gain amplifier with offset cancellation
Ahmed Emira, Edgar Sánchez-Sinencio
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
Magdy A. El-Moursy, Eby G. Friedman
GLVLSI
2003
IEEE
157views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Optimum wire sizing of RLC interconnect with repeaters
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be co...
Magdy A. El-Moursy, Eby G. Friedman
GLVLSI
2003
IEEE
125views VLSI» more  GLVLSI 2003»
13 years 10 months ago
MuTaTe: an efficient design for testability technique for multiplexor based circuits
Rolf Drechsler, Junhao Shi, Görschwin Fey