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    GLVLSI
    2005
    IEEE
    85views VLSI» more  GLVLSI 2005»
    Utilizing don't care states in SAT-based bounded sequential problems
    13 years 10 months ago
    Utilizing don't care states in SAT-based bounded sequential problems
    Download  www.informatik.uni-bremen.de
    Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
    Sean Safarpour, Görschwin Fey, Andreas G. Ven...
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    GLVLSI
    2005
    IEEE
    103views VLSI» more  GLVLSI 2005»
    Causal probabilistic input dependency learning for switching model in VLSI circuits
    13 years 10 months ago
    Causal probabilistic input dependency learning for switching model in VLSI circuits
    Download  www.eng.usf.edu
    Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...
    Nirmal Ramalingam, Sanjukta Bhanja
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    GLVLSI
    2005
    IEEE
    186views VLSI» more  GLVLSI 2005»
    An FPGA design of AES encryption circuit with 128-bit keys
    13 years 10 months ago
    An FPGA design of AES encryption circuit with 128-bit keys
    Download  www.lsi-cad.com
    This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
    Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
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    GLVLSI
    2005
    IEEE
    144views VLSI» more  GLVLSI 2005»
    On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
    13 years 10 months ago
    On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
    Download  www.ece.rochester.edu
    —On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
    Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
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    GLVLSI
    2005
    IEEE
    199views VLSI» more  GLVLSI 2005»
    Interconnect delay minimization through interlayer via placement in 3-D ICs
    13 years 10 months ago
    Interconnect delay minimization through interlayer via placement in 3-D ICs
    Download  www.ece.rochester.edu
    The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
    Vasilis F. Pavlidis, Eby G. Friedman
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    GLVLSI
    2005
    IEEE
    99views VLSI» more  GLVLSI 2005»
    An empirical study of crosstalk in VDSM technologies
    13 years 10 months ago
    An empirical study of crosstalk in VDSM technologies
    Download  atrak.usc.edu
    We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
    Shahin Nazarian, Massoud Pedram, Emre Tuncer
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    GLVLSI
    2005
    IEEE
    152views VLSI» more  GLVLSI 2005»
    A high speed and leakage-tolerant domino logic for high fan-in gates
    13 years 10 months ago
    A high speed and leakage-tolerant domino logic for high fan-in gates
    Download  online.sfsu.edu
    Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
    Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
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    GLVLSI
    2005
    IEEE
    81views VLSI» more  GLVLSI 2005»
    Fine-grain leakage optimization in SRAM based FPGAs
    13 years 10 months ago
    Fine-grain leakage optimization in SRAM based FPGAs
    Download  www.eecs.northwestern.edu
    Somsubhra Mondal, Seda Ogrenci Memik
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    GLVLSI
    2005
    IEEE
    124views VLSI» more  GLVLSI 2005»
    SOFTENIT: a methodology for boosting the software content of system-on-chip designs
    13 years 10 months ago
    SOFTENIT: a methodology for boosting the software content of system-on-chip designs
    Download  www.cs.ucr.edu
    Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
    Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
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    GLVLSI
    2005
    IEEE
    120views VLSI» more  GLVLSI 2005»
    3D module placement for congestion and power noise reduction
    13 years 10 months ago
    3D module placement for congestion and power noise reduction
    Download  www.gtcad.gatech.edu
    3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
    Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
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