Sciweavers

GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
13 years 10 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
GLVLSI
2005
IEEE
83views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Diagnosing multiple transition faults in the absence of timing information
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Ven...
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
13 years 10 months ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
13 years 10 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
13 years 10 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg
GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...
GLVLSI
2005
IEEE
125views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Low-power circuits using dynamic threshold devices
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
Paul Beckett