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ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
13 years 9 months ago
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
Kenneth L. Shepard, Dae-Jin Kim
ICCAD
1999
IEEE
62views Hardware» more  ICCAD 1999»
13 years 9 months ago
A scalable substrate noise coupling model for mixed-signal ICs
A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be ...
Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
ICCAD
1999
IEEE
75views Hardware» more  ICCAD 1999»
13 years 9 months ago
Functional timing optimization
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
Alexander Saldanha
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
13 years 9 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
13 years 9 months ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
ICCAD
1999
IEEE
93views Hardware» more  ICCAD 1999»
13 years 9 months ago
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing a...
Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Ham...
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
13 years 9 months ago
A framework for testing core-based systems-on-a-chip
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
13 years 9 months ago
An approach for improving the levels of compaction achieved by vector omission
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
13 years 9 months ago
Transient sensitivity computation for transistor level analysis and tuning
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Tuyen V. Nguyen, Peter O'Brien, David W. Winston
ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
13 years 9 months ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai