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ICCD
2004
IEEE
64views Hardware» more  ICCD 2004»
14 years 1 months ago
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs
Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing...
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 1 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
Yau Chin, John Sheu, David Brooks
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 1 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 1 months ago
Thermal-Aware Clustered Microarchitectures
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
Pedro Chaparro, José González, Anton...
ICCD
2004
IEEE
105views Hardware» more  ICCD 2004»
14 years 1 months ago
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
Donald Chai, Andreas Kuehlmann
ICCD
2004
IEEE
71views Hardware» more  ICCD 2004»
14 years 1 months ago
On-Chip Transparent Wire Pipelining
Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from bein...
Mario R. Casu, Luca Macchiarulo
ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 1 months ago
Functional Illinois Scan Design at RTL
This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compressi...
Ho Fai Ko, Nicola Nicolici
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 1 months ago
Extending the Applicability of Parallel-Serial Scan Designs
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...
Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
ICCD
2004
IEEE
131views Hardware» more  ICCD 2004»
14 years 1 months ago
3D Processing Technology and Its Impact on iA32 Microprocessors
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
Bryan Black, Donald Nelson, Clair Webb, Nick Samra
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 1 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...