Sciweavers

ISCAS
2007
IEEE
135views Hardware» more  ISCAS 2007»
13 years 11 months ago
Application-Specific Instruction Generation for SOC Processors
Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
13 years 11 months ago
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
Xiang Gao, Eric A. M. Klumperink, Bram Nauta
ISCAS
2007
IEEE
90views Hardware» more  ISCAS 2007»
13 years 11 months ago
Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse Response
— A method is presented to synthesize wideband linear-phase FIR filters with a piecewise-polynomial-sinusoidal impulse response. The proposed method is based on merging the earl...
Raija Lehto, Tapio Saramäki, Olli Vainio
ISCAS
2007
IEEE
124views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Brief Overview of the Complex Biological and Engineering Networks
— Over the last few decades, complex networks have been intensively studied throughout many fields of science, especially in biological and engineering sciences. This paper brie...
Jinhu Lu, Derong Liu
ISCAS
2007
IEEE
86views Hardware» more  ISCAS 2007»
13 years 11 months ago
Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier
Timothy K. Horiuchi, Dorielle Tucker, Kevin Boyle,...
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
13 years 11 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
13 years 11 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
ISCAS
2007
IEEE
129views Hardware» more  ISCAS 2007»
13 years 11 months ago
ECC Processor with Low Die Size for RFID Applications
Abstract— This paper presents the design of a special purpose processor with Elliptic Curve Digital Signature Algorithm (ECDSA) functionality. This digital signature generation d...
Franz Fürbass, Johannes Wolkerstorfer