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ISPD
1998
ACM
101views Hardware» more  ISPD 1998»
13 years 10 months ago
Greedy wire-sizing is linear time
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
Chris C. N. Chu, D. F. Wong
ISPD
1998
ACM
74views Hardware» more  ISPD 1998»
13 years 10 months ago
LIBRA - a library-independent framework for post-layout performance optimization
Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng
ISPD
1998
ACM
192views Hardware» more  ISPD 1998»
13 years 10 months ago
On convex formulation of the floorplan area minimization problem
It is shown that the oorplan area minimization problem can be formulated as a convex programming problem with the numbers of variables and constraints signi cantly less than those...
Temo Chen, Michael K. H. Fan
ISPD
1998
ACM
86views Hardware» more  ISPD 1998»
13 years 10 months ago
Calculation of ramp response of lossy transmission lines using two-port network functions
In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a pure capacitive load. The approach is based on the two-port ...
Payam Heydari, Massoud Pedram
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
13 years 10 months ago
CHDStd - application support for reusable hierarchical interconnect timing views
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
ISPD
1998
ACM
79views Hardware» more  ISPD 1998»
13 years 10 months ago
On wirelength estimations for row-based placement
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniqu...
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mant...
ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 10 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He
ISPD
1998
ACM
91views Hardware» more  ISPD 1998»
13 years 10 months ago
Estimation of maximum current envelope for power bus analysis and design
In this paper we present an input pattern independent method to compute the maximum current envelope, which is an upper bound over all possible current waveforms drawn by a circui...
Sudhakar Bobba, Ibrahim N. Hajj
ISPD
1998
ACM
187views Hardware» more  ISPD 1998»
13 years 10 months ago
The ISPD98 circuit benchmark suite
From 1985-1993, the MCNC regularly introduced and maintained circuit benchmarks for use by the Design Automation community. However, during the last five years, no new circuits h...
Charles J. Alpert