ISPD
2010
ACM
13 years 11 months ago
2010
ACM
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...