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ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
10 years 8 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
10 years 8 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ISPD
2010
ACM
173views Hardware» more  ISPD 2010»
10 years 8 months ago
B-escape: a simultaneous escape routing algorithm based on boundary routing
Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, ...
ISPD
2010
ACM
195views Hardware» more  ISPD 2010»
10 years 8 months ago
Density gradient minimization with coupling-constrained dummy fill for CMP control
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
ISPD
2010
ACM
157views Hardware» more  ISPD 2010»
10 years 8 months ago
SafeChoice: a novel clustering algorithm for wirelength-driven placement
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...
Jackey Z. Yan, Chris Chu, Wai-Kei Mak
ISPD
2010
ACM
177views Hardware» more  ISPD 2010»
10 years 8 months ago
Skew management of NBTI impacted gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
Ashutosh Chakraborty, David Z. Pan
ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
10 years 8 months ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
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