Sciweavers

DAC
2010
ACM
13 years 8 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
ANCS
2007
ACM
13 years 8 months ago
An improved algorithm to accelerate regular expression evaluation
Modern network intrusion detection systems need to perform regular expression matching at line rate in order to detect the occurrence of critical patterns in packet payloads. Whil...
Michela Becchi, Patrick Crowley
PLDI
1994
ACM
13 years 8 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
IPPS
1996
IEEE
13 years 8 months ago
A Memory Controller for Improved Performance of Streamed Computations on Symmetric Multiprocessors
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
Sally A. McKee, William A. Wulf
INFOCOM
1998
IEEE
13 years 8 months ago
Doubling Memory Bandwidth for Network Buffers
Memory bandwidth is frequently a limiting factor in the design of high-speed switches and routers. In this paper, we introduce a buffering scheme called ping-pong buffering, that ...
Youngmi Joo, Nick McKeown
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
13 years 9 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
MICRO
2006
IEEE
79views Hardware» more  MICRO 2006»
13 years 10 months ago
Fair Queuing Memory Systems
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
ISCAS
2006
IEEE
96views Hardware» more  ISCAS 2006»
13 years 10 months ago
Frame-level data reuse for motion-compensated temporal filtering
— Motion-compensated temporal filtering (MCTF) is an open-loop prediction scheme, so the frame-level data reuse for MCTF is possible. In this paper, we propose two general frame...
Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang...
IMSCCS
2006
IEEE
13 years 10 months ago
CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline
Depth traffic occupies a major portion of 3D graphics memory bandwidth. In order to reduce depth reading, we propose employing a low-resolution depth buffer, namely CoarseZ buffer...
Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua...
ICMCS
2006
IEEE
137views Multimedia» more  ICMCS 2006»
13 years 10 months ago
An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder
This paper proposes an efficient reference frame storage scheme for HDTV VLSI decoder to reduce external memory bandwidth requirement. The proposed scheme consists of the pixel du...
Peng Zhang, Wen Gao, Di Wu, Don Xie