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MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
13 years 9 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
13 years 9 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 9 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
MICRO
1997
IEEE
93views Hardware» more  MICRO 1997»
13 years 9 months ago
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine
In this paper we investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are bene ts to using the decoupling para...
G. P. Jones, Nigel P. Topham
MICRO
1997
IEEE
128views Hardware» more  MICRO 1997»
13 years 9 months ago
Run-Time Spatial Locality Detection and Optimization
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
MICRO
1997
IEEE
84views Hardware» more  MICRO 1997»
13 years 9 months ago
Procedure Placement Using Temporal Ordering Information
Nicholas C. Gloy, Trevor Blackwell, Michael D. Smi...
MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
13 years 9 months ago
Path-Based Next Trace Prediction
Quinn Jacobson, Eric Rotenberg, James E. Smith
MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
13 years 9 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
13 years 9 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
11
Voted
MICRO
1997
IEEE
76views Hardware» more  MICRO 1997»
13 years 9 months ago
A Framework for Balancing Control Flow and Predication
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
David I. August, Wen-mei W. Hwu, Scott A. Mahlke