Sciweavers

MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
13 years 11 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
13 years 11 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
13 years 11 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
13 years 11 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
13 years 11 months ago
Copy or Discard execution model for speculative parallelization on multicores
The advent of multicores presents a promising opportunity for speeding up sequential programs via profile-based speculative parallelization of these programs. In this paper we pr...
Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta
MICRO
2008
IEEE
116views Hardware» more  MICRO 2008»
13 years 11 months ago
Power reduction of CMP communication networks via RF-interconnects
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyu...
MICRO
2008
IEEE
121views Hardware» more  MICRO 2008»
13 years 11 months ago
Temporal instruction fetch streaming
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
Michael Ferdman, Thomas F. Wenisch, Anastasia Aila...
MICRO
2008
IEEE
88views Hardware» more  MICRO 2008»
13 years 11 months ago
Facelift: Hiding and slowing down aging in multicores
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
Abhishek Tiwari, Josep Torrellas
MICRO
2008
IEEE
148views Hardware» more  MICRO 2008»
13 years 11 months ago
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
Ramazan Bitirgen, Engin Ipek, José F. Mart&...
MICRO
2008
IEEE
124views Hardware» more  MICRO 2008»
13 years 11 months ago
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits
Rootkits have become a growing concern in cyber-security. Typically, they exploit kernel vulnerabilities to gain root privileges of a system and conceal malware’s activities fro...
Vikas R. Vasisht, Hsien-Hsin S. Lee