Sciweavers

Share
ASPDAC
2006
ACM
108views Hardware» more  ASPDAC 2006»
10 years 3 months ago
Spec-based flip-flop and latch repeater planning
Abstract-- Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient t...
Man Chung Hon
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
10 years 4 months ago
Optimal buffered routing path constructions for single and multiple clock domain systems
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
10 years 5 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
10 years 5 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
books