ASPDAC
2006
ACM
13 years 8 months ago
2006
ACM
Abstract-- Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient t...
ICCAD
2002
IEEE
13 years 10 months ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...