Sciweavers

Share
ISCAS
2005
IEEE

A distributed FIFO scheme for on chip communication

10 years 4 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasitic effects. On chip communication now requires multiple clock cycles for signal propagation between communicating modules/components. Repeater insertion is widely used to improve global interconnect delays. We propose having distributed first in first out buffers to facilitate communication between components/modules of highly integrated systems, such as system on chip. This stateful scheme has very good tolerance for voltage and temperature variations. The buffer control circuitry is self-timed and allows for ease of interfacing in multiple domain clock designs. In this paper, we present the buffer and its associated control circuits that
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
Comments (0)
books