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TC
2008
10 years 1 months ago
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Xiaogang Qiu, Michel Dubois
AES
2005
Springer
137views Cryptology» more  AES 2005»
10 years 1 months ago
Design of a multimedia processor based on metrics computation
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...
Nader Ben Amor, Yannick Le Moullec, Jean-Philippe ...
ASPDAC
2001
ACM
130views Hardware» more  ASPDAC 2001»
10 years 5 months ago
Area/delay estimation for digital signal processor cores
Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and...
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa...
CF
2007
ACM
10 years 5 months ago
Performance/area efficiency in chip multiprocessors with micro-caches
This paper proposes the use of very small instruction caches, called micro-caches (
Michela Becchi, Mark A. Franklin, Patrick Crowley
FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
10 years 5 months ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
10 years 5 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
CODES
2000
IEEE
10 years 5 months ago
A method to derive application-specific embedded processing cores
The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to...
Olivier Hébert, Ivan C. Kraljic, Yvon Savar...
MICRO
2002
IEEE
122views Hardware» more  MICRO 2002»
10 years 6 months ago
Microarchitectural denial of service: insuring microarchitectural fairness
Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date,...
Dirk Grunwald, Soraya Ghiasi
FPL
2003
Springer
128views Hardware» more  FPL 2003»
10 years 6 months ago
A Generic Architecture for Integrated Smart Transducers
Abstract. A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
10 years 6 months ago
Instruction Set Emulation for Rapid Prototyping of SoCs
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware be...
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenst...
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