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2003
IEEE

Instruction Set Emulation for Rapid Prototyping of SoCs

11 years 10 months ago
Instruction Set Emulation for Rapid Prototyping of SoCs
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware behaviour of the emulated processor core is reproduced cycle accurately. This requires the use of hardware and software components. The hardware component consists of a board containing a VLIW processor and FPGAs. The software component is an instruction set simulator of the core running on the VLIW processor. The FPGAs are used for emulating the SoC bus of this processor core. This way the simulation of an instruction set of a processor core has been extended to a real emulation of this core that can be used for rapid prototyping.
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenst
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DATE
Authors Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel
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