Sciweavers

MTV
2005
IEEE
101views Hardware» more  MTV 2005»
13 years 10 months ago
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time...
Paolo Bernardi, Michelangelo Grosso, Maurizio Reba...
CODES
2005
IEEE
13 years 10 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
13 years 11 months ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
DATE
2007
IEEE
93views Hardware» more  DATE 2007»
13 years 11 months ago
Testing in the year 2020
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
13 years 11 months ago
Process variation aware thread mapping for Chip Multiprocessors
Abstract—With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiproce...
Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut ...
ARC
2009
Springer
165views Hardware» more  ARC 2009»
13 years 11 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont