DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Reconfigurable Systems-on-Chip (SoC) consist of large Field-Programmable Gate-Arrays (FPGAs) and standard processors. The reconfigurable logic can be used for application-specific...
ARC
2007
Springer
13 years 8 months ago
2007
Springer
This paper presents the implementation of an environment for the evolution of one-dimensional cellular automata using a reconfigurable logic device. This configware is aimed at eva...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we descri...
FCCM
1999
IEEE
13 years 8 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
FCCM
2000
IEEE
13 years 9 months ago
2000
IEEE
Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic [Hauck98]. Howeve...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
FPL
2003
Springer
13 years 9 months ago
2003
Springer
Abstract. Hybrid Hall effect (HHE) devices are a new class of reconfigurable logic devices that incorporate ferromagnetic elements to deliver nonvolatile operation. A single HHE de...
FCCM
2003
IEEE
13 years 9 months ago
2003
IEEE
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...