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MICRO
2010
IEEE
186views Hardware» more  MICRO 2010»
13 years 2 months ago
SAFER: Stuck-At-Fault Error Recovery for Memories
As technology scaling poses a threat to DRAM scaling due to physical limitations such as limited charge, alternative memory technologies including several emerging non-volatile me...
Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Sriniv...
TCAD
2008
96views more  TCAD 2008»
13 years 4 months ago
An Implicit Approach to Minimizing Range-Equivalent Circuits
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
Yung-Chih Chen, Chun-Yao Wang
DFT
2006
IEEE
148views VLSI» more  DFT 2006»
13 years 6 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
13 years 10 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...