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DATE
2005
IEEE
115views Hardware» more  DATE 2005»
13 years 10 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
SCESM
2006
ACM
257views Algorithms» more  SCESM 2006»
13 years 10 months ago
Test ready UML statechart models
The dynamic behavior of systems is best described by Finite-state machines. Generation of executable tests from behavioral models such as UML Statecharts offers benefits such as s...
P. V. R. Murthy, P. C. Anitha, M. Mahesh, Rajesh S...
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
13 years 10 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
13 years 10 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
OOPSLA
2007
Springer
13 years 10 months ago
Randoop: feedback-directed random testing for Java
RANDOOP FOR JAVA generates unit tests for Java code using feedback-directed random test generation. Below we describe RANDOOP’s input, output, and test generation algorithm. We ...
Carlos Pacheco, Michael D. Ernst
MODELS
2007
Springer
13 years 10 months ago
Deriving Input Partitions from UML Models for Automatic Test Generation
Abstract. In this paper, we deal with model-based automatic test generation. We show how to use UML state machines, UML class diagrams, and OCL expressions to automatically derive ...
Stephan Weißleder, Bernd-Holger Schlingloff
KBSE
2007
IEEE
13 years 10 months ago
Directed test generation using symbolic grammars
We present CESE, a tool that combines exhaustive enumeration of test inputs from a structured domain with symbolic execution driven test generation. We target programs whose valid...
Rupak Majumdar, Ru-Gang Xu
DATE
2007
IEEE
84views Hardware» more  DATE 2007»
13 years 11 months ago
On test generation by input cube avoidance
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
Irith Pomeranz, Sudhakar M. Reddy
KBSE
2008
IEEE
13 years 11 months ago
Predicting Effectiveness of Automatic Testing Tools
—Automatic white-box test generation is a challenging problem. Many existing tools rely on complex code analyses and heuristics. As a result, structural features of an input prog...
Brett Daniel, Marat Boshernitsan