Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
The dynamic behavior of systems is best described by Finite-state machines. Generation of executable tests from behavioral models such as UML Statecharts offers benefits such as s...
P. V. R. Murthy, P. C. Anitha, M. Mahesh, Rajesh S...
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
RANDOOP FOR JAVA generates unit tests for Java code using feedback-directed random test generation. Below we describe RANDOOP’s input, output, and test generation algorithm. We ...
Abstract. In this paper, we deal with model-based automatic test generation. We show how to use UML state machines, UML class diagrams, and OCL expressions to automatically derive ...
We present CESE, a tool that combines exhaustive enumeration of test inputs from a structured domain with symbolic execution driven test generation. We target programs whose valid...
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
—Automatic white-box test generation is a challenging problem. Many existing tools rely on complex code analyses and heuristics. As a result, structural features of an input prog...