ICTAI
2002
IEEE
13 years 9 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
ICSE
2003
IEEE-ACM
13 years 9 months ago
2003
IEEE-ACM
This paper presents a model checking-based approach to data flow testing. We characterize data flow oriented coverage criteria in temporal logic such that the problem of test ge...
FATES
2003
Springer
13 years 9 months ago
2003
Springer
Use of model-checking approaches for test generation from requirement models have been proposed by several researchers. These approaches leverage the witness (or counter-example) ...
FATES
2003
Springer
13 years 9 months ago
2003
Springer
Generating effective tests and inferring likely program specifications are both difficult and costly problems. We propose an approach in which we can mutually enhance the tests and...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
UML
2004
Springer
13 years 10 months ago
2004
Springer
We describe the tools and interfaces created by the AGEDIS project, a European Commission sponsored project for the creation of a methodology and tools for automated model driven ...
FATES
2004
Springer
13 years 10 months ago
2004
Springer
We present an extension of Tretmans’ theory and algorithm for test generation for input-output transition systems to real-time systems. Our treatment is based on an operational i...
MTV
2005
IEEE
13 years 10 months ago
2005
IEEE
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architec...