Sciweavers

IPPS
2010
IEEE
13 years 1 months ago
A low cost split-issue technique to improve performance of SMT clustered VLIW processors
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...
Manoj Gupta, Fermín Sánchez, Josep L...
CODES
2001
IEEE
13 years 8 months ago
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
Cagdas Akturan, Margarida F. Jacome
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
13 years 9 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
DSD
2007
IEEE
122views Hardware» more  DSD 2007»
13 years 11 months ago
Energy Based Design Space Exploration of Multiprocessor VLIW Architectures
Today energy is an important factor in designing a multiprocessor system. The overall goal of this work is to propose a methodology for design space exploration of VLIW multiproce...
Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksr...
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 1 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 1 months ago
Speculative Trace Scheduling in VLIW Processors
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
14 years 1 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 4 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
DAC
2002
ACM
14 years 5 months ago
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto,...