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TCAD
2002
72views more  TCAD 2002»
8 years 11 months ago
Wire width planning for interconnect performance optimization
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
Jason Cong, David Zhigang Pan
VLSISP
2008
108views more  VLSISP 2008»
8 years 12 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
TCAD
2008
106views more  TCAD 2008»
8 years 12 months ago
Track Routing and Optimization for Yield
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
DAC
1997
ACM
9 years 4 months ago
Wire Segmenting for Improved Buffer Insertion
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
Charles J. Alpert, Anirudh Devgan
ICCAD
1997
IEEE
118views Hardware» more  ICCAD 1997»
9 years 4 months ago
Global interconnect sizing and spacing with consideration of coupling capacitance
This paper presents an ef´Čücient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang P...
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