ISCA 2012 - PDF Preprint Papers

ISCA 2012 International Symposium on Computer Architecture

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ISCA
2012
IEEE

333views Hardware» more ISCA 2012»

Reducing memory reference energy with opportunistic virtual caching

11 years 8 hour ago

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Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...

Arkaprava Basu, Mark D. Hill, Michael M. Swift

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Id	Views	Title	Status

1	333	Reducing memory reference energy with opportunistic virtual caching	claim
2	320	Viper: Virtual pipelines for enhanced reliability	claim
3	302	Scale-out processors	claim
4	281	LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems	claim
5	280	A case for random shortcut topologies for HPC interconnects	claim
6	279	Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems	claim
7	274	The dynamic granularity memory system	claim
8	270	Revisiting hardware-assisted page walks for virtualized systems	claim
9	262	Boosting mobile GPU performance with a decoupled access/execute fragment processor	claim
10	261	RAIDR: Retention-aware intelligent DRAM refresh	claim
11	260	A case for exploiting subarray-level parallelism (SALP) in DRAM	claim
12	248	Watchdog: Hardware for safe and secure manual memory management and full memory safety	claim
13	244	Scheduling heterogeneous multi-cores through performance impact estimation (PIE)	claim
14	243	BlockChop: Dynamic squash elimination for hybrid processor architecture	claim
15	243	Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures	claim
16	242	Side-channel vulnerability factor: A metric for measuring information leakage	claim
17	237	BOOM: Enabling mobile memory based low-power server DIMMs	claim
18	234	PARDIS: A programmable memory controller for the DDRx interfacing standards	claim
19	233	iGPU: Exception support and speculative execution on GPUs	claim
20	232	RADISH: Always-on sound and complete race detection in software and hardware	claim
21	224	A first-order mechanistic model for architectural vulnerability factor	claim
22	218	CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures	claim
23	218	Towards energy-proportional datacenter memory with mobile DRAM	claim
24	218	The Yin and Yang of power and performance for asymmetric hardware and managed software	claim
25	212	TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks	claim
26	208	Harmony: Collection and analysis of parallel block vectors	claim
27	191	VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors	claim

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