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ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
13 years 8 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
13 years 8 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
13 years 8 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 8 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
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ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
13 years 8 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...