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112
Voted
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 7 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
118
Voted
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 7 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
156
Voted
CAV
2006
Springer
117views Hardware» more  CAV 2006»
15 years 7 months ago
Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop
e Abstraction and Refinement Loop Himanshu Jain1,2, Franjo Ivanci
Himanshu Jain, Franjo Ivancic, Aarti Gupta, Ilya S...
124
Voted
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 7 months ago
Workload Characterization Model for Tasks with Variable Execution Demand
The analysis of real-time properties of an embedded system usually relies on the worst-case execution times (WCET) of the tasks to be executed. In contrast to that, in real world ...
Alexander Maxiaguine, Simon Künzli, Lothar Th...