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ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
15 years 10 months ago
TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
Joakim Byg, Kenneth Yrke Jørgensen, Jir&iac...
ASPDAC
2007
ACM
67views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Synthesis of Reversible Sequential Elements
Min-Lun Chuang, Chun-Yao Wang
ASPDAC
2007
ACM
123views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
Communication exploration has become a critical step during SoC design. Researchers in the CAD community have proposed fast and efficient techniques for comprehensive design space ...
Pramod Chandraiah, Junyu Peng, Rainer Dömer
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
15 years 10 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 10 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...