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ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 10 months ago
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
Hao Fang, Chenguang Tong, Xu Cheng
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic
112
Voted
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Communication Architecture Synthesis of Cascaded Bus Matrix
Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Ch...
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Retargetable Software Timing Analyzer Using Architecture Description Language
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Pra...