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ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
APSCC
2007
IEEE
15 years 10 months ago
A One-Way File Replica Consistency Model in Data Grids
Chao-Tung Yang, Wen-Chi Tsai, Tsui-Ting Chen, Chin...
ASPDAC
2009
ACM
190views Hardware» more  ASPDAC 2009»
15 years 10 months ago
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
ASPDAC
2009
ACM
184views Hardware» more  ASPDAC 2009»
15 years 10 months ago
FastRoute 4.0: global router with efficient via minimization
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
Yue Xu, Yanheng Zhang, Chris Chu