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    DAC
    2007
    ACM
    112views Computer Architecture» more  DAC 2007»
    Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
    16 years 8 months ago
    Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
    Download  dns.ime.tsinghua.edu.cn
    In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
    Tao Li, Zhiping Yu
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    DAC
    2008
    ACM
    168views Computer Architecture» more  DAC 2008»
    Faster symmetry discovery using sparsity of symmetries
    16 years 8 months ago
    Faster symmetry discovery using sparsity of symmetries
    Download  www.eecs.umich.edu
    Many computational tools have recently begun to benefit from the use of the symmetry inherent in the tasks they solve, and use general-purpose graph symmetry tools to uncover this...
    Paul T. Darga, Karem A. Sakallah, Igor L. Markov
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    DAC
    2008
    ACM
    143views Computer Architecture» more  DAC 2008»
    Tera-scale computing and interconnect challenges
    16 years 8 months ago
    Tera-scale computing and interconnect challenges
    Download  www.cc.gatech.edu
    Jerry Bautista
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    DAC
    2008
    ACM
    142views Computer Architecture» more  DAC 2008»
    On the role of timing masking in reliable logic circuit design
    16 years 8 months ago
    On the role of timing masking in reliable logic circuit design
    Download  www.eecs.umich.edu
    Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
    Smita Krishnaswamy, Igor L. Markov, John P. Hayes
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    DAC
    2008
    ACM
    109views Computer Architecture» more  DAC 2008»
    An integrated nonlinear placement framework with congestion and porosity aware buffer planning
    16 years 8 months ago
    An integrated nonlinear placement framework with congestion and porosity aware buffer planning
    Download  www.cerc.utexas.edu
    Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
    Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
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