CMOS analog iterative decoders using margin propagation circuits

Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS analog decoders uses MOS transistors biased in weak inversion which limits -1 their speed of operation. In this paper a novel analog decoding network is presented which can operate with MOS transistor :-2 biased both in weak and strong inversion. The principle of operation is based on margin propagation algorithm which -3 requires only addition,subtraction and thresholding operation 0 which can be easily implemented in analog VLSI. A current -4 mode implementation of the decoder is proposed which operates 5 directly in log-likelihood space. This not only improves the speed of convergence for iterative decoding but also enhances the 6 dynamic range of the decoder. Simulation based on a simple tail-biting trellis is presented that demonstrate the decoding - e e e characteristic and speed of operation of the propose...

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: S. Chakrabartty
• Keywords: Analog, Analog Iterative Decoders, ISCAS 2006, Mos Transistor