Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

92

Voted

ISPD
2006
ACM

91views Hardware» more ISPD 2006»

Variation tolerant buffered clock network synthesis with cross links

15 years 8 months ago

Variation tolerant buffered clock network synthesis with cross links

Download www.sigda.org

Anand Rajaram, David Z. Pan

Real-time Traffic

Hardware | ISPD 2006 |

claim paper

Related Content

» Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

» Discrete Buffer and Wire Sizing for LinkBased NonTree Clock Networks

» MeshWorks A Comprehensive Framework for Optimized Clock Mesh Network Synthesis

» Performance Evaluation of Elastic GALS Interfaces and Network Fabric

Post Info
More Details (n/a)

Added	14 Jun 2010
Updated	14 Jun 2010
Type	Conference
Year	2006
Where	ISPD
Authors	Anand Rajaram, David Z. Pan

Comments (0)