Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

131

ISCAS
2003
IEEE

77views Hardware» more ISCAS 2003»

Inductive interconnect width optimization for low power

15 years 10 months ago

Inductive interconnect width optimization for low power

Download www.ece.rochester.edu

The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the width of inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error of less than 6% is presented. For a speci c set of line parameters and resistivities, the power is reduced by almost 80% as compared to a minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.

Magdy A. El-Moursy, Eby G. Friedman

Real-time Traffic

ISCAS 2003 | Optimum Line Width | Total Transient Power | Transient Power Dissipation |

claim paper

Related Content

» Inductive properties of highperformance power distribution grids

» Low power repeaters driving RLC interconnects with delay and bandwidth constraints

» Line width optimization for interdigitated powerground networks

» Optimum wire sizing of RLC interconnect with repeaters

» Interconnectaware highlevel synthesis for low power

» Practical repeater insertion for low power what repeater library do we need

» QuasiResonant Interconnects A Low Power Design Methodology

» Onchip inductance cons and pros

» INTACTE an interconnect area delay and energy estimation tool for microarchitectural explo...

Post Info
More Details (n/a)

Added	04 Jul 2010
Updated	04 Jul 2010
Type	Conference
Year	2003
Where	ISCAS
Authors	Magdy A. El-Moursy, Eby G. Friedman

Comments (0)