Hardware Support for Control Transfers in Code Caches

Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when control is transferred from one cached superblock to another, especially via register-indirect jumps. The basic problem is that instruction addresses in the code cache are different from those in the original program binary. Therefore, performance for register-indirect jumps depends on the ability to translate efficiently from source binary PC values to code cache PC values. We analyze several key aspects of superblock chaining and find that a conventional baseline code cache with software jump target prediction results in 14.6% IPC loss versus the original binary. We identify the inability to use a conventional return address stack as the most significant performance limiter in code cache systems. We introduce a modified software prediction technique that reduces the

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Ho-Seop Kim, James E. Smith
• Keywords: Baseline Code Cache, Code Cache, Code Cache Systems, Hardware, MICRO 2003