Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

87

Voted

ISLPED
2003
ACM

78views Hardware» more ISLPED 2003»

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

15 years 8 months ago

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Download www.ece.uwaterloo.ca

Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram

Real-time Traffic

ISLPED 2003 |

claim paper

Related Content

» An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Bas...

» Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits

» Architecture and circuit techniques for lowthroughput energyconstrained systems across tec...

» Unified P4 powerperformanceprocessparasitic fast optimization of a NanoCMOS VCO

» Why area might reduce power in nanoscale CMOS

» Gate replacement techniques for simultaneous leakage and aging optimization

» Congestionaware power grid optimization for 3D circuits using MIM and CMOS decoupling capa...

» Elements of low power design for integrated systems

» A Novel VariationTolerant Keeper Architecture for HighPerformance LowPower Wide FanIn Dyna...

Post Info
More Details (n/a)

Added	05 Jul 2010
Updated	05 Jul 2010
Type	Conference
Year	2003
Where	ISLPED
Authors	Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar

Comments (0)